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TSL3301 102 x 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER
TAOS026 - FEBRUARY 2001
D D D D D D D D
102 x 1 Sensor Element Organization 300 Dots-per-Inch Pixel Pitch High Sensitivity On-Chip 8-Bit Analog-to-Digital Conversion Three-Zone Programmable Offset (Dark Level) and Gain High Speed Serial Interface 1 MHz Pixel Rate Single 3-V to 5.5-V Supply
(TOP VIEW)
SCLK VDD SDIN SDOUT
1 2 3 4
8 7 6 5
NC GND GND NC
NC - No internal connection
Description
The TSL3301 is a high-sensitivity 300-dpi, linear optical sensor array with integrated 8-bit analog-to-digital converters. The array consists of 102 pixels, each measuring 85 m (H) by 77 m (W) and spaced on 85 m centers. Associated with each pixel is a charge integrator/amplifier and sample-hold circuit. All pixels have concurrent integration periods and sampling times. The array is split into three 34-pixel zones, with each zone having programmable gain and offset levels. Data communication is accomplished through a three-wire serial interface. Intended for use in high performance, cost-sensitive scanner applications, the TSL3301 is based on a linear sensor array die that has expanded capability, including multi-die addressing and cascade options. Please contact TAOS for additional information on die and multi-die package availability.
Functional Block Diagram
PIXEL ARRAY WITH INTEGRATORS AND S-H (51-bit shift register)
PIXCLK
SI
HOLD
ZERO
LEFT EVEN
RIGHT ODD
RIGHT EVEN
IREF
8 SCLK 5 SDIN SDOUT DIGITAL I/O AND CONTROL 3
DB<7:0> ADDR<4:0> READ WRITE SECTOR BIAS BLOCK OUTPUT CHARGE-TOVOLTAGE CONVERTER WITH PROGRAMMABLE GAINS AND OFFSETS VREF IREF
RESET/SAMPLE START ADCLK DUAL 8-BIT SA ADC
VREF IREF
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Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) 673-0759
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Terminal Functions
TERMINAL NAME GND SCLK SDIN SDOUT VDD NO. 6, 7 1 3 4 2 I I O I/O Ground System clock input for serial I/O and all internal logic. Serial data input. Data is clocked in on the rising edge of SCLK. Serial data output. Data is clocked out on the falling edge of SCLK. Positive supply voltage. DESCRIPTION
Detailed Description
The TSL3301 is a 102 x 1 linear optical array with onboard A/D conversion. It communicates over a serial digital interface and operates over a 3 V to 5.5 V range. The array is divided into three 34-pixel zones (left, center, and right), with each zone having programmable gain and offset (dark signal) correction. The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging on a pixel generates a photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity (Ee) on that pixel and to the integration time (tint). At maximum programmed gain, one LSB corresponds to approximately 300 electrons. Integration, sampling, output, and reset of the integrators are performed by the control logic in response to commands input via the SDIN pin. Data is read out on the SDOUT pin. A normal sequence of operation consists of a pixel reset (RESET), start of integration (STARTInt), integration period, sampling of integrators (SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit. Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command or reset by a RESET command. Gain adjustment is controlled by three 5-bit DACs, one for each of the the three zones. Table 1 lists the gain settings and the corresponding pixel values. Offset is affected by the gain setting and may have to be adjusted after gain changes are made. Offset correction is controlled by three 8-bit sign-magnitude DACs and is performed in the analog domain prior to the digital conversion. There is a separate offset DAC for each of the three zones. Codes 0h - 7Fh correspond to positive offset values and codes 80h - FFh correspond to negative offset values. The offset correction is proportional to the gain setting. At minimal gain, one LSB of the offset DAC corresponds to approximately 1/3 LSB of the device output, and at maximum gain, to about 1 LSB of the device output. Note that the gain and offset registers are in indeterminate states after power up and must be set by the controller as required.
Sign-magnitude is a binary representation in which the most significant bit (MSB) is used to represent the sign of the number, with the remaining bits representing the magnitude. An MSB of 1 indicates a negative number.
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TAOS026 - FEBRUARY 2001
Table 1. Gain Settings and Results
GAIN CODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RELATIVE GAIN 1 1.02 1.05 1.07 1.09 1.12 1.15 1.18 1.21 1.24 1.27 1.31 1.34 1.38 1.43 1.47 2.17 2.22 2.27 2.33 2.38 2.44 2.50 2.56 2.63 2.70 2.78 2.86 2.94 3.03 3.13 % INCREASE GAIN CODE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RELATIVE GAIN 1.52 1.57 1.62 1.68 1.74 1.81 1.88 1.96 2.05 2.14 2.24 2.35 2.48 2.61 2.77 2.94 % INCREASE 3.23 3.33 3.45 3.57 3.70 3.85 4.00 4.17 4.35 4.55 4.76 5.00 5.26 5.56 5.88 6.25
Serial interface
The serial interface follows a USART format, with start bit, 8 data bits and one or more stop bits. Data is clocked in synchronously on the rising edge of SCLK and clocked out on the falling edge of SCLK. Stop bits are not required on the input. When clocking data out continuously (i.e., reading out pixels) there will be one stop bit between data words. The receive and transmit state machines are independent, which means commands can be issued while reading data. This feature allows starting new integration cycles while reading data. Note that this allows undefined conditions so care must be taken not to issue commands that will cause outputs (such as register read) while reading out data. For instance, issuing a register read command while reading out image data will result in garbage out. Likewise, it is possible to change offset and gain registers during a readout, which can give unpredictable results. It is not necessary to have a continuously active clock, but a minimum of 6 clocks is required after any command has been issued to ensure that the corresponding internal logic actions have been completed. When reading register contents, there will be a 4-clock delay from the completion of the REGRead command before the register contents are output. When reading out pixel values, there will be a 44-clock delay from completion of the READPixel command until the first pixel data is output. When sampling pixel information it is necessary to have 22 clocks to complete the pixel reset cycle (see Imaging below).
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TSL3301 102 x 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER
Register address map
The TSL3301 contains seven registers as defined in Table 2. Data in these registers may be written to or read from using the REGWrite and REGRead commands. Three registers control the gain of the analog-to-digital converters (ADC). Three other registers allow the offset of the system to be adjusted. Together the gain and offset registers are used to maximize the achievable dynamic range. Table 2. Register Address Map
ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x1F REGISTER DESCRIPTION Left (pixels 0-33) offset Left (pixels 0-33) gain Center (pixels 34-67) offset Center (pixels 34-67) gain Right (pixels 68-101) offset Right (pixels 68-101) gain Mode REGISTER WIDTH 8 5 8 5 8 5 8
The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset correction.) These registers allow the user to maximize the dynamic range achievable in the given system. The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device. Users should always write zeros into the production test and multichip control bits.
7 0x1F P2
6 0
5 0
4 SLP
3 P1
2 P0
1 C1
0 C0 MODE
SLP = Sleep Mode: 1 places device into sleep mode
C1, C0 selects multichip options (should be written 0) P2 to P0 are factory test bits (should be written 0)
0 places device in normal operating mode
Figure 1. Mode Register Bit Assignments
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TAOS026 - FEBRUARY 2001
Command description
The TSL3301 is a slave device that reacts strictly to commands received from the digital controller. These commands cause the device to perform functions such as reset, integrate, sample, etc. Table 3 summarizes the command types and formats and Table 4 lists the command set for the TSL3301. Each command is described in more detail below. Table 3. Command Type and Format Summary
COMMAND TYPE Action command Register write < Command byte > < Command byte > < Data byte > FORMAT
Table 4. TSL3301 Command Set
COMMAND IRESET RESET DETReset STARTInt SAMPLEInt READPixel ABORTPixel READHold READHoldNStart REGWrite REGRead Interface Reset Reset Integration and read blocks Reset determine unique address block Start pixel integration Stop light integration and sample results Dump serial the contents of each sampled integrator Abort any READPixel operation in progress Combination of SAMPLEInt and READPixel commands Combination of SAMPLEInt, READPixel and STARTInt commands Write a gain, offset, or mode register Read a gain, offset, or mode register DESCRIPTION
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PROGRAMMING INFORMATION
A minimum of 6 clock cycles is required after any command to ensure that the internal logic actions have been completed.
Reset Commands
Reset commands are used to put the TSL3301 into a known state. IRESET -- Interface Initialization
Encoding: Break Character (10 or more consecutive start bits, or zeros) The commands vary in length from one to three bytes. IRESET initializes the internal state machine that keeps track of which command bytes have been received. This command should be first and given only once after power-up to synchronize the TSL3301 internal command interpreter. An alternative is to issue three successive RESET commands.
RESET -- Main Reset
Encoding: 0x1b: <0001_1011>
RESET resets most of the internal control logic of the TSL3301 and any READPixel command currently in progress is aborted. RESET puts the pixel integrators into the auto-zero/reset state. Any values that were being held in the array's sample/hold circuits are lost.
NOTE: The value on the SDOUT pin is not guaranteed from the time power is applied until 30 clocks after the first RESET command is issued.
Pixel Action Commands
Pixel action commands allow the user to control pixel integration and reading of pixel data. STARTInt -- Start Integration
Encoding: 0x08: <0000_1000>
STARTInt causes each pixel to leave the reset state and to start integrating light. The actual execution of STARTInt is delayed until the pixel reset cycle has been completed. (See imaging below.) SAMPLEInt -- Stop Integration
Encoding: 0x10: <0001_0000>
SAMPLEInt causes each pixel to store its integrator's contents into a sample and hold circuit. Also, the Integrator is returned to the reset state. Twenty-two clock cycles are necessary to complete the pixel reset cycle. READPixel -- Read Pixel Data
Encoding: 0x02: <0000_0010>
READPixel causes the sampled value of each pixel to be converted to an 8-bit digital value that is clocked out on the SDOUT pin. The LSB is the first data bit, which is preceded by a START bit (logic 0) and followed by a STOP bit (logic 1). Each pixel in the device is presented on SDOUT starting from pixel 00 and completes with pixel 101. There is a 44-clock cycle delay from the completion of the READPixel command until the first pixel data is output.
Gain and offset registers are used to adjust the ADC converter to maximize dynamic range and should be programmed prior to invoking the READPixel command.
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ABORTPixel -- Abort Pixel Data Read
Encoding: 0x19: <0001_1001>
ABORTPixel is an optional command that stops a READPixel command during its execution. It also causes pixel integration to terminate and the device to enter the auto-zero/reset state. Any values that were being held in the array's sample/hold circuits are lost. READHold -- Sample and Read Combination
Encoding: 0x12: <0001_0010>
READHold is a macro command that combines both the SAMPLEInt and READPixel commands into a single command. 22 clock cycles are necessary to complete the pixel reset cycle. READHoldNStart Combination
Encoding: 0x16: <0001_0110>
READHold is a macro command that combines the SAMPLEInt, READPixel, and StartInt commands into a single command. 22 clock cycles are necessary to complete the pixel reset cycle.
Register Commands
The register commands provide the user the capability of setting gain and offset corrections for each of the three zones of pixels. a4-a0 refer to the register address as given in Table 2. REGWrite -- Write a Gain/Offset/Mode Register
Encoding (2 bytes): 0x40 : <010a4_a3a2a1a0>
REGWrite writes a value into either a gain, offset, or mode register. The 5-bit address of the register is encoded into the lower 5 bits of the command byte (the first byte). A second byte, which contains the data to be written, follows the command byte. REGRead -- Read a Gain/Offset/Mode Register
Encoding: 0x60: <011a4_a3a2a1a0>
REGRead reads the value previously stored in a gain, offset, or mode register. The 5-bit address of the register is encoded into the lower 5 bits of the command byte. Following receipt of the REGRead command, the device places the contents of the selected register onto the SDOUT pin, LSB first.
There is a 4-clock cycle delay from the completion of the REGRead command until the register contents are output.
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OPERATION
Initialization Sequence
After powering on the device, a minimum of 10 clocks with SDIN held high must be received by the TSL3301 to clear the receiver logic so that a start bit will be detected correctly. The control logic may then be cleared by either issuing an IRESET command (break character) or 3 RESET (0x1b) commands. An additional 30 clocks must be received by the device to assure the state of SDOUT.
Sleep Mode
The device can be put into a power down or sleep mode by writing a 0x10 to the mode register. This turns off all the analog circuitry on the chip. Normal operation is restored by writing a 0x00 to the mode register. The analog circuitry will require a minimum of 1 millisecond to recover from the sleep mode. Note that putting the device in the sleep mode does not affect the logic states of the machine. If, for example, a READPixel command is issued, the device will respond but the resulting data will be meaningless. Also note that 0x00 and 0x40 are the only two legitimate user programmable values for the single-chip version of the TSL3301. Other values may put the device into a non-operational mode.
For minimum sleep mode current consumption, voltage levels on logic inputs must be at either VDD or ground.
Imaging
After powering up the device and completing the initialization sequence, it is necessary to allow a minimum of 1 millisecond for the internal analog circuitry to settle. This delay is also required when coming out of the sleep mode. Issuing a STARInt (0x08) command will release the pixel integrators from the reset state. After an appropriate delay to integrate the image, the pixel data may be sampled by issuing a SAMPLEInt (0x10) command and then read out by issuing a READPixel (0x02) command. A STARTInt command can be issued anytime after the SAMPLEInt command is issued to start another cycle. Thus, it is possible to be reading out one sample while integrating the next. However, the sampled data from the previous SAMPLEInt must be completely read out before the next SAMPLEInt command is issued. The compound commands READHold (0x12) and READHoldNStart ((0x16) are shortcut commands to simplify the imaging sequence. It is important to note that a pixel reset sequence is initiated with the receipt of a SAMPLEInt, READHold, or READHoldNStart command. The next integration sequence cannot start until the pixel reset sequence has been completed, which requires 22 clocks AFTER the receipt of one of these commands. These clocks can be used to clock commands or data into or out of the device.
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Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 to +10 mA Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA to 20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25_C to 85_C ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN Supply voltage, VDD High-level input voltage at SCLK, SDIN, VIH Low-level input voltage at SCLK, SDIN, VIL Power supply ripple, 100 kHz sawtooth waveform Input clock (SCLK) rise time, 10% to 90% Operating junction temperature, TJ Maximum clock frequency, fSCLK 0 3 2 NOM 5 MAX 5.5 VDD 0.8 60 30 70 10 UNIT V V V mVp-p ns C MHz
Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VDD = 5 V VOH High-level High level output voltage SDOUT voltage, VDD = 3 3 V 3.3 VOL Low-level Low level output voltage, SDOUT voltage IO = 50 A IO = 4 mA A/D active IDD VIL VIH IIH IIL Su ly Supply current Low-level input voltage (SCLK, SDIN) High-level input voltage (SCLK, SDIN) High-level input current (SCLK, SDIN) Low-level input current (SCLK, SDIN) VI = VDD VI = 0 2 10 10 A/D inactive Sleep mode IO = 50 A IO = 4 mA IO = 50 A IO = 4 mA MIN 4.5 TYP 4.95 4.6 2.9 2.7 0.01 0.4 11 6 17 11 10 0.8 mA V V 0.1 V V MAX UNIT
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Light-to-Digital Transfer Characteristics at VDD = 5 V, TJ = 25C, p = 660 nm, tint = 250 s (unless otherwise noted)
PARAMETER A-to-D converter resolution Gain register = 00000b Full-scale Full scale reference Gain register = 11111b For converter only, does not include photodiode characteristics 0 Offset register = 00000000b Gain register = 00000b, see Note 1 Dark signal nonuniformity (DSNU) Gain register = 11111b, see Note 1 Offset register = 00000000b Gain register = 00000b Ee = 11.3 W/cm2 Gain register = 11111b Ee = 3.77 W/cm2 Ee = 11.3 W/cm2, See Notes 2 and 3 160 200 200 4% 128 Gain register = 00000b Programmable offset step size Dark-level change with temperature Differential nonlinearity Integral nonlinearity Gain register = 00000b Dark level noise Gain register = 11111b Gain register = 11111b 0C < TJ < 70C 0.5 1.5 2 0.5 1 0.5 1.5 LSB LSB LSB LSB LSB 5% TEST CONDITIONS MIN TYP 8 3.6 1.24 150 7 20 5 10 14 240 LSB LSB 30 LSB MAX UNIT Bits nJ/cm2 ppm/C
Full-scale reference temperature sensitivity Gain register = 00000b Average dark level offset dark-level Gain register = 11111b
Average white level output
Photo-response non-uniformity (PRNU) Programmable offset steps
NOTES: 1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not illuminated. 2. PRNU does not include DSNU. 3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN fmax tw(CLKH) tw(CLKL) tsu th Maximum clock frequency Clock high pulse duration Clock low pulse duration Input setup time Input hold time 10 30 30 20 20 NOM MAX UNIT MHz ns ns ns ns
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
PARAMETER tr tf td Ci Rise time, output Fall time, output Delay from clock edge to data-out stable Input pin capacitance CL = 20 pF TEST CONDITIONS MIN TYP 10 10 20 10 MAX UNIT ns ns ns pF
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SCLK
tw(CLKH) tw(CLKL) th tsu
VIH VIL VIH VIL
SDIN
Figure 2. TSL3301 Input Timing Requirements
VIH SCLK td VIL VOH SDOUT VOL
Figure 3. TSL3301 Output Switching Characteristics
SCLK
SDIN
Start
B0
B1
B2
B3
B4
B5
B6
B7
Stop
Serial Input Data Format
SCLK
SDOUT
Start
B0
B1
B2
B3
B4
B5
B6
B7
Stop
Serial Output Data Format
Figure 4. TSL3301 Serial I/O
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TYPICAL CHARACTERISTICS
PHOTODIODE SPECTRAL RESPONSIVITY
1.2 TA = 25C 1.0 Relative Responsivity Normalized to 660 nm
0.8
0.6
0.4
0.2
0 300
500
700 900 - Wavelength - nm
1100
Figure 5. TSL3301 Photodiode Spectral Response
APPLICATION INFORMATION
Normal Sequence
A typical programming sequence for the TSL3301 device appears below:
Send(IRESET); Send(RESET); Calibration Cycle * * while(1) { for(i=0;i<=2;i++) {/* for each pixel page */ Write page gain register Write page offset register Read page gain register and verify (optional) Read page offset register and verify (optional) } } Send(STARTInt); DelayIntegrationTime(); /* wait for appropriate time interval to elapse */ Send(SAMPLEInt); Send(READPixel);
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MECHANICAL INFORMATION
This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated with an electrically nonconductive clear plastic compound.
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 SCLK VDD SDIN SDOUT NC GND GND NC
0.430 (10,92) 0.410 (10,41) Centerline of Pin 1 Nominally Lies between pixels 6 and 7 0.390 (9,91) 8 5
0.310 (7,87) 0.290 (7,37) 0.017 (0,43) 0.260 (6,60) 0.240 (6,10) 0.030 (0,76) D NOM 0.135 (3,43) 0.115 (2,93) 0.175 (4,45) 0.155 (3,94) 1 0.060 (1,52) 0.040 (1,02) 8 Places 4
C L
C (pixel) L
0.020 (0,51) R NOM 4 Places 8 MAX TYP 0.053 (1,35) 0.043 (1,09)
10 TYP
0.012 (0,30) 0.008 (0,20)
Seating Plane 105 90 8 Places 0.016 (0,41) 0.014 (0,36) 0.067 (1,70) 0.053 (1,35) 0.150 (3,81) 0.125 (3,18) 0.025 (0,64) 0.015 (0,38) 0.100 (2,54) T.P.
0.040 (1,02) 0.020 (0,52)

True position when unit is installed Minimum flat-optical-surface length NOTES: A. All linear dimensions are in inches and parenthetically in millimeters. B. This drawing is subject to change without notice. C. Index of refraction of clear plastic is 1.55.
Figure 6. Packaging Configuration
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PRODUCTION DATA -- information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER'S RISK.
TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
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